In general, in switching mode power supply (SMPS) applications, current through an inductive load is typically sensed indirectly by monitoring a current through a power transistor wherein the transistor is coupled to the inductive load and the inductive load is further coupled to an input supply voltage. This sensed current signal through the power transistor is used for cycle-by-cycle current limiting and for current mode control. However, during the power transistor turn-on transition, a current spike occurs due to parasitic capacitances primarily occurring due to inductor or transformer interwinding capacitances and power transistor output capacitances. It is well known in the art that this leading edge current spike must be filtered out to prevent the control circuit, which is responsive to the current sense signal, from responding to the current spike.
One simple solution to this problem is to generate a blanking signal that disables the control circuitry for a fixed period of time after the power transistor is turned on. However, a problem with this solution is that the specific time period of the blanking signal must be designed for the worst case current spike pulse width. As a result, the duration of the blanking signal is typically too long for many applications.
Another solution to the problem is to use external timing elements to optimally set the blanking time for each specific application. However, a problem with this solution is that it increases the integrated circuit's pin count as well as the number of external components.
Another solution is described in detail in an IEEE conference proceedings article on Applied Power Electronics Conference (APEC) entitled "A Monolithic Boost Converter for Telecom Applications" by F. J. DE Stasi and T. S. Szepesi wherein FIG. 8 shows an adaptive blanking circuit. However, this adaptive blanking circuit does not work well under short circuit conditions and further the adaptive blanking circuit is quite complex in circuitry.
Hence, there exists a need for an improved leading edge blanking circuit having minimum circuitry and for providing a blanking signal whose pulse width adapts to various operating conditions such as high initial drain voltages, low initial drain voltages, or a drain short circuit condition.